The present invention relates generally to a microcomputer and, more particularly, to a single chip microcomputer comprising a data processing system together with a system resource having different data bus sizes or cycles.
In order to improve the general-purpose properties of a microcomputer to be developed, there are taken counter-measures for enhancing the general-purpose properties of either the internal functions or the external interface functions of the microcomputer.
In order to enhance the general-purpose properties of the internal functions of the microcomputer, the following counter-measures are taken. The internal memory to be programmed is made of an electrically programmable read only memory (as will be referred to as "EPROM"); The number of bits in the general-purpose registers themselves to be packaged in the microcomputer are increased. The internal peripheral circuits of the microprocessor may include a free running timer, an analog-to-digital converter, a pulse width modulation (i.e., PWM) timer, a serial communication interface circuit or a direct memory access controller.
In order to enhance the external interface function, a wait control circuit is packaged in the microprocessor so as to facilitate an interface with a low speed memory such as a dynamic random access memory.
A dynamic bus sizing function is given to the microprocessor. The dynamic bus sizing function gives the microcomputer dynamically a 4-bit interface or an 8-bit interface. This allows a data exchange between an external device having a data bus width with an intrinsic 4 or 8 bits and an external microcomputer of 16-bit interface, i.e., the number of external data terminals is 16 bits. In other words, the function to selectively change the bus sizing operations dynamically according to the various external conditions is called the dynamic bus sizing function.
This dynamic bus sizing function is important for dropping the cost of a data processor system having the microcomputer and for augmenting the degree of freedom for designing the aforementioned data processor system.
The present invention has been conceived in the course of enhancing the general-purpose properties of the aforementioned dynamic bus sizing function and pursuing high-speed operations.